When designing a digital energy provide resembling enhance energy issue correction (PFC), have you ever ever seen a present oscillate prefer it does in **Determine 1**?

**Determine 1 **Present oscillation occurs in PFC stage.

It’s possible you’ll suppose that this unstable oscillation is attributable to a too-fast management band, so that you cut back the proportional achieve (Kp) and integral achieve (Ki) of the proportional-integral (PI) controller and considerably cut back the cross frequency. Then the oscillation disappears.

However is that the perfect resolution? The decrease current-loop bandwidth reduces the management velocity, however it’s possible you’ll discover that the overall harmonic distortion (THD) check fails. And typically the oscillation seems once more when your supply impedance is a little bit bit giant.

Is there one other doable reason for this instability? How are you going to obtain the perfect management bandwidth with sufficient part margin? Let’s analyze the digital management loop intimately, to see how is that this potential mistake launched. And, it’s possible you’ll verify whether or not this similar occurs in your management firmware.

**MCU-based digital management**

**Determine 2** illustrates an MCU-based digital management system.

**Determine 2 **An MCU-based digital management system.

The management loop contains an analog-to-digital converter (ADC) for sampling the item present/voltage, a digital controller for producing the alter worth, and a pulse-width modulator (PWM) for executing the adjustment, altering the goal present/voltage by altering the obligation or frequency.

ADC sampling in a switched-mode energy provide (SMPS) is commonly on the center factors of two switching cycles, which not solely avoids noise disturbances from switching, but in addition will get the typical present worth of the ability inductor in steady conduction mode (CCM).

The digital controller is calculated in an interrupt service routine (ISR) and could possibly be triggered synchronously with the PWM output. The set off occasion could possibly be one among these occurrences: the PWM’s ‘COUNTER’ equals ‘ZERO’, ‘PERIOD’, or a selected worth ’CMP’.

It isn’t doable to replace the PWM instantly when the controller completes all calculations, however the PWM registers should be loaded by shadow registers at a devoted second, resembling when the PWM counter equals ‘ZERO’ or ‘PERIOD’. If the PWM values are modified whereas the counter is rising or falling, it is rather doable to generate false PWM motion, lacking pulses, or duplicating pulses.

Not like an analog management system, digital management is executed by the sampling frequency, and there should be a delay time (*T _{d}*) from sampling to reloading a brand new worth to the PWM. PWM modification is applied by adjusting the flipping moments, which occurs as soon as with single-edge modulation (depend up/depend down mode), and occurs twice with dual-edge modulation (depend up-down mode). So, the minimal

*T*can be one switching cycle

_{d}*T*, (as proven in

_{s}**Determine 3a**) or one-half switching cycle

*T*, (as proven in

_{s}/2**Determine 3b**), relying on the modulation reloading frequency that you simply select.

**Determine 3 **Minimal delay time launched by PWM adjusting: (a) up mode, (b) up-down mode.

**Determine 4**, *T _{d}* could be expressed as

*e*

^{-sxT}*in its switch perform, which would scale back the part margin. In fact, when the part margin is lower than 45 levels, the system will change into unstable and oscillation will happen.*

^{d}**Determine 4 **The affect of time delay within the Bode plot.

**A possible code ****mistake in digital management implementation**

With right execution, the minimal *T _{d}* is one switching cycle

*T*half switching cycle

_{s}*T*. However, for those who haven’t thought-about the consequence of ADC, ISR and PWM reloading, it’s doable that extending the management delay to a couple of switching cycle might cut back part margin and result in instability.

_{s}/2For instance, in **Determine 5** the ADC’s ISR set off and PWM reload begin on the similar second, when the PWM counter equals zero.

Though all blocks execute on the similar time, are you able to anticipate *T _{d}* to be zero on this case? Completely not!

**Determine 5 **Instance of incorrect code introducing a bigger delay time.

It is because each the ADC conversion and ISR calculation require far a couple of MCU clocking cycle—the ADC conversion nonetheless hasn’t accomplished when the ISR reads the ADC end result. Thus, the ISR will get the ‘previous’ pattern worth for calculating, and the calculation for the most recent worth is delayed till the following switching cycle. After the completion of the ISR calculation, the brand new PWM worth is just written into the shadow register, which can be reloaded within the subsequent switching cycle. In actuality the overall management delay of *T _{d}* can be two switching cycles, or

*2 x T*.

_{s}Apart from the examples proven right here, different implementations might introduce comparable prolonged management delays—for instance, for those who put the ADC worth studying after the controller calculation within the ISR code, or for those who add an N-cycles algorithm common earlier than calculating the controller.

As proven in **Determine 6, **after we set the GAIN cross frequency at round 3 kHz with the false implementation of Determine 5 the part margin is 41.68 levels. That is lower than 45 levels, and the choke present has important oscillation, just like the waveform of Determine 1, so we’re compelled to scale back the cross frequency to decrease than 2 kHz; then the iTHD turns worse and fail the necessities.

**Determine 6 **Bode plot with the incorrect code implementation.

**Resolution**

You possibly can simply repair this drawback by transferring the ADC conversion to the second of counter = interval and have PWM reloading happen within the subsequent counter = interval, as proven in **Determine 7**.

**Determine 7 **Lowering the management delay with code enchancment.

The management delay can be decreased to at least one switching cycle. The part margin will increase considerably, and the present oscillation disappears, as proven in **Determine 8** and **Determine 9**.

**Determine 8 **Bode plot with improved code.

**Determine 9 **Waveform with improved code.

**Conclusion**

The management delay in a digital implementation, from ADC sampling to PWM adjustment, will cut back the part margin and trigger oscillation. When tackling this subject, think about the consequence of ADC sampling, controller calculation and PWM reloading. A well-organized management scheme can reduce the delay to one-half, or one switching cycle, which will increase the part margin and loop bandwidth.

**References**

TIDA-010062: 1-kW, 80 Plus titanium, GaN CCM totem pole bridgeless PFC and half-bridge LLC reference design, https://www.ti.com/tool/TIDA-010062

*Guo Desheng, system software engineer of energy design companies at Texas Devices*

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